#Constraint
set CLK_PHASE_0_SRC "dummy_clk4x"
set EDGES {1 3 5}
set CLK_PHY_PORT "clk4x"
set PERIOD [expr 0.833 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] set PHY_CLK_PERIOD $PERIOD set PHY_HALF [expr 0.5 * $PHY_CLK_PERIOD] set PHY_QUARTER [expr 0.25 * $PHY_CLK_PERIOD]
set CTLR_CLK_PERIOD [expr 2 * $PHY_CLK_PERIOD]
set PHY_DDL_CLK_PERIOD [expr 0.2 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE]
create_clock [get_ports $CLK_PHY_PORT ] -name dummy_clk4x -period $PHY_HALF -waveform "0 $PHY_QUARTER"
set clk_dqs_pin0 [cdn_get_pin inst_data_path_tb/inst_write_path_tb/inst_clk_wrdqs_base_delay_macro/inst_wrdqs_base_delay_line/inst_exit_inv/hic_dnt_inv/${NEG_OUTPUT} inst_data_path_tb/inst_write_path_tb/inst_clk_wrdqs_base_delay_macro/inst_wrdqs_base_delay_line/base_delay_out]
create_generated_clock -name clk_dqs_phase_3 -source $CLK_PHY_PORT -edges $EDGES -edge_shift "$THREE_EIGHTH $THREE_EIGHTH $THREE_EIGHTH" -add -master_clock [get_clocks $CLK_PHASE_0_SRC ] $clk_dqs_pin0
create_generated_clock -name clk_dqs_phase_7 -source $CLK_PHY_PORT -edges $EDGES -edge_shift "$SEVEN_EIGHTH $SEVEN_EIGHTH $SEVEN_EIGHTH" -add -master_clock [get_clocks $CLK_PHASE_0_SRC ] $clk_dqs_pin0
Some source 2 clk frequency 1.2GHz
#Command reference
Models multiple generated clocks on the same source when multiple clocks must fan into the source pin. Ideally, one generated clock must be specified for each clock that fans into the master pin. Specify this option with the -name and -master_clock options.
By default, the software creates one generated clock at the pin by using the fastest clock present on the source pin as the master clock. However, use the -add option to specify a different clock name for each generated clock when used with the -master_clock option. Subsequently, you can use this clock name for setting other constraints, such as the set_false_path command and the set_input_delay command.
Pei 